The recent revolution in telecommunications has led to a corresponding revolution in electronics. Wireless communications devices are now as plentiful as the rotary telephone of yesteryears. One key component of many wireless circuits is the delta sigma controlled fractional N frequency synthesizer. Such a circuit allows for the synthesizing of almost any required signal frequency. As part of this component, a phase frequency detector (PFD) receives an input reference signal with a known frequency and a variable input signal, known as a divider input, with a variable frequency determined by dividing a VCO (voltage controlled oscillator) frequency. The PFD outputs a signal that is proportional to the difference in phase between the input reference signal and the divider input. This output can then be used to increase-or decrease the VCO frequency to minimize the phase difference. This feedback arrangement is called a phase lock loop or a PLL.
Current PFD designs suffer from what is commonly termed a “deadzone”. When the frequency synthesizer is in lock, the phase difference between the reference and the divider input is very close to zero. Thus, the output (or outputs as the PFD may have more than one output) should not be active or, if they are, the pulses produced should be very narrow. For small phase errors close to zero, due to delays and uncontrollable circumstances, it is not possible to create a complete pulse at the output of the PFD. This results in a flat or non-linear section in the PFD transfer curve normally termed a deadzone. While not very serious for integer-N synthesizers, this can result in increased fractional-N spur levels for delta sigma controlled fractional-N frequency synthesizers.
As such, there is therefore a need for systems and components which avoid the above problems. It is therefore an object of the present invention to mitigate if not overcome the shortcomings of the prior art.